1. Technical Field
The present invention generally relates to integrated circuit technology. In particular, the present invention relates to methods and systems for detecting manufacturing defects and logical errors within integrated circuits. More particularly the present invention relates to methods and systems for detecting manufacturing defects and logical errors within complementary circuits.
2. Description of the Related Art
As processor speeds continue to climb, designers are forced to achieve higher circuit speeds in order to accommodate the increased demand in processor performance. Many circuit design techniques are presently being utilized to achieve such high speeds. For example, dynamic logic is increasingly being utilized in integrated circuit designs to increase processor speed. Dynamic logic, however, while suitable for increasing the speed of integrated circuits, is error prone and costly to debug when failing. Consequently, fast static logic families are becoming more prevalent in industry today to counteract the issues involved with dynamic logic. Such static logic families are typically dual-rail in nature, meaning that they produce true and complementary output signals in parallel. Examples of such families include Double Pass-Transistor Logic (DPL), Differential Cascode Voltage Switch with Pass-Gate (DCVSPG), and Complementary Pass-Transistor Logic (CPL).
However testing problems involved with complementary logic circuits quickly arise when implementing such circuits as integrated circuit chips. For example, nodes may become "stuck," "open," or shorted to other signals due to manufacturing errors, causing output signals of the wrong value or state. Such incorrect values can cause problems in subsequently connected logic stages, leading to a significant reduction in testing coverage. Any subsequently connected logic stages coupled "downstream" in an integrated circuit cannot expect such defective complementary logic circuits to supply the correct complementary logic signals, thus causing floating nodes or value contention (i.e., indeterminate state) within the complementary logic circuits. Such indeterminate results can lead to a failure to expose a defective circuit during testing, resulting in later logic errors during circuit use.
Presently, techniques do not exist for specifically identifying errors within complementary logic circuits. Based on the foregoing, those skilled in the art will appreciate that a need exists for a method and system which would allow designers to implement on-chip testing circuits which specifically indicate that associated complementary circuits contain manufacturing defects or logical errors.